1. Field of the Invention
The invention relates in general to multi-processor computers, and in particular to a computer having a high-speed multi-processor architecture which is highly scalable and which can operate in both SIMD and MIMD modes.
2. Related Art
Multiprocessor architectures, which are capable of performing both SIMD mode and MIMD mode operations are known in the art. In SIMD (Single Instruction set Multiple Data set) mode operations, a single instruction source, e.g., a memory device, typically drives multiple parallel processors, which each execute the same operation thread in synchrony upon different data sets. The instructions are typically delivered from the instruction source to the multiple processors via an instruction bus common to all processors. In order for parallel processors to have simultaneous access to the shared instruction source without contention, a high-speed common instruction bus must be must be used. As additional processors are added to a particular SIMD design, the speed requirements of the common instruction bus become greater such that the scalability of the design is limited by the significant economic expense of the required high-speed instruction bus. And, such designs cannot be scaled up to include more processors than can be supported by the fastest bus available within current bus technology.
In MIMD (Multiple Instruction sets Multiple Data sets) mode operations, on the other hand, all parallel processors potentially execute different operation threads on different data sets. In such operations, access to a shared memory is not required, and the use of a shared memory rather tan isolated local memories associated with each processor is actually a hindrance during MIMD operations because that shared memory can become saturated. And, this problem typically increases as more parallel processors are used in a shared memory design, thereby reducing the scalability of the design.
Because of the differences in requirements for SIMD versus MIMD mode operations, different topologies for interconnecting multiple processors with memories have been provided in the prior art depending on which mode of operation is required. And, various schemes have been used for providing multiprocessor architectures which can operate in both SIMD and MIMD modes. U.S. Pat. No. 5,212,777 to Gove et al. describes multiprocessor architectures for reconfigurable SIMD/MIMD mode operations wherein a cross bar switch is provided between a series of processors and a series of memories. The cross bar switch acts as a multiplexor and permits the processor-to-memory interconnection scheme to be changed depending upon which mode of operations is being performed. However, as such designs are scaled up to include a large number of parallel processors, the switching requirements of the cross-bar switch increase dramatically and the cost of providing such a cross-bar switch becomes prohibitive.
U.S. Pat. No. 5,355,508 to Kan discloses a parallel processor system for mixed SIMD/MIMD mode operation wherein a first series of processors and associated memories are configured for and dedicated to SIMD operations while a second series of processors and associated memories are configured for and dedicated to MIMD operations. The SIMD and MIMD processors are connected via a common bus to a shared global memory. A system controller allocates operations which lend themselves to SIMD processing to the SIMD processors and operations which lend themselves to MIMD processing to the MIMD processors. However, the system disclosed by Kan suffers from inefficiency during a period when, e.g., a long series of MIMD operations are performed because, during that time, the dedicated SIMD) processors are not being used.
Many prior art multi-processor devices which support MIMD mode operations comprise a "cluster" architecture in which a series of processors share a common bus and each processor has access to the I/O ports and RAM resources of the other processors. However, multi-processor designs which use cluster architectures often suffer from undesirable processor contention for global memory and I/O. Further, cluster architectures often require expensive high-speed memory and are limited in that they generally cannot support SIMD) mode operations.